`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   23:12:09 11/22/2013
// Design Name:   Level_Buffer
// Module Name:   G:/Xilinx_Proj/H_264_test/Level_buffer_test.v
// Project Name:  H_264_test
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Level_Buffer
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module Level_buffer_test;

	// Inputs
	reg Clk;
	reg Rst;
	reg Sig_level_write;
	reg [3:0] Level_num;
	reg [8:0] Level_value;

	// Outputs
	wire [8:0] Level_0;
	wire [8:0] Level_1;
	wire [8:0] Level_2;
	wire [8:0] Level_3;
	wire [8:0] Level_4;
	wire [8:0] Level_5;
	wire [8:0] Level_6;
	wire [8:0] Level_7;
	wire [8:0] Level_8;
	wire [8:0] Level_9;
	wire [8:0] Level_10;
	wire [8:0] Level_11;
	wire [8:0] Level_12;
	wire [8:0] Level_13;
	wire [8:0] Level_14;
	wire [8:0] Level_15;
	reg [6:0]cnt;
	// Instantiate the Unit Under Test (UUT)
	Level_Buffer uut (
		.Clk(Clk), 
		.Rst(Rst), 
		.Sig_level_write(Sig_level_write), 
		.Level_num(Level_num), 
		.Level_value(Level_value), 
		.Level_0(Level_0), 
		.Level_1(Level_1), 
		.Level_2(Level_2), 
		.Level_3(Level_3), 
		.Level_4(Level_4), 
		.Level_5(Level_5), 
		.Level_6(Level_6), 
		.Level_7(Level_7), 
		.Level_8(Level_8), 
		.Level_9(Level_9), 
		.Level_10(Level_10), 
		.Level_11(Level_11), 
		.Level_12(Level_12), 
		.Level_13(Level_13), 
		.Level_14(Level_14), 
		.Level_15(Level_15)
	);

	initial begin
		// Initialize Inputs
		Clk = 0;
		Rst = 0;
		Sig_level_write = 0;
		Level_num = 0;
		Level_value = 0;

		// Wait 100 ns for global reset to finish
		#100;
        cnt = 0;  
		// Add stimulus here
		#50 Rst = 0;
		#50 Rst = 1;
		// Add stimulus here

	end
      
always #20 Clk=~Clk;
always @(posedge Clk or negedge Rst) begin
		if(!Rst) begin
			cnt <= 0;
			Sig_level_write <=0;
		end
		else begin
			case(cnt)
			0:begin	  
				Sig_level_write <= 1;
				Level_num <= 0;
				Level_value <= 6'b111111;
				cnt <= cnt+1;
			end	
			1:begin
				Sig_level_write <= 0;
				cnt <= cnt+1;
			end
			2:begin	  
				Sig_level_write <= 1;
				Level_num <= 1;
				Level_value <= 6'b111111;
				cnt <= cnt+1;
			end	
			3:begin
				Sig_level_write <= 0;
				cnt <= cnt+1;
			end
			4:begin	  
				Sig_level_write <= 1;
				Level_num <= 2;
				Level_value <= 6'b111111;
				cnt <= cnt+1;
			end	
			5:begin
				Sig_level_write <= 0;
				cnt <= cnt+1;
			end
			6:begin	  
				Sig_level_write <= 1;
				Level_num <= 3;
				Level_value <= 6'b111111;
				cnt <= cnt+1;
			end	
			7:begin
				Sig_level_write <= 0;
				cnt <= cnt+1;
			end
			8:begin	  
				Sig_level_write <= 1;
				Level_num <= 4;
				Level_value <= 6'b111111;
				cnt <= cnt+1;
			end	
			9:begin
				Sig_level_write <= 0;
				cnt <= cnt+1;
			end
			10:begin	  
				Sig_level_write <= 1;
				Level_num <= 5;
				Level_value <= 6'b111111;
				cnt <= cnt+1;
			end	
			11:begin
				Sig_level_write <= 0;
				cnt <= cnt+1;
			end
			12:begin	  
				Sig_level_write <= 1;
				Level_num <= 6;
				Level_value <= 6'b111111;
				cnt <= cnt+1;
			end	
			13:begin
				Sig_level_write <= 0;
				cnt <= cnt+1;
			end
			14:begin	  
				Sig_level_write <= 1;
				Level_num <= 7;
				Level_value <= 6'b111111;
				cnt <= cnt+1;
			end	
			15:begin
				Sig_level_write <= 0;
				cnt <= cnt+1;
			end
			16:begin	  
				Sig_level_write <= 1;
				Level_num <= 8;
				Level_value <= 6'b111111;
				cnt <= cnt+1;
			end	
			17:begin
				Sig_level_write <= 0;
				cnt <= cnt+1;
			end
			18:begin	  
				Sig_level_write <= 1;
				Level_num <= 9;
				Level_value <= 6'b111111;
				cnt <= cnt+1;
			end	
			19:begin
				Sig_level_write <= 0;
				cnt <= cnt+1;
			end
			20:begin	  
				Sig_level_write <= 1;
				Level_num <= 10;
				Level_value <= 6'b111111;
				cnt <= cnt+1;
			end	
			21:begin
				Sig_level_write <= 0;
				cnt <= cnt+1;
			end
			22:begin	  
				Sig_level_write <= 1;
				Level_num <= 11;
				Level_value <= 6'b111111;
				cnt <= cnt+1;
			end	
			23:begin
				Sig_level_write <= 0;
				cnt <= cnt+1;
			end
			24:begin	  
				Sig_level_write <= 1;
				Level_num <= 12;
				Level_value <= 6'b111111;
				cnt <= cnt+1;
			end	
			25:begin
				Sig_level_write <= 0;
				cnt <= cnt+1;
			end
			26:begin	  
				Sig_level_write <= 1;
				Level_num <= 13;
				Level_value <= 6'b111111;
				cnt <= cnt+1;
			end	
			27:begin
				Sig_level_write <= 0;
				cnt <= cnt+1;
			end
			28:begin	  
				Sig_level_write <= 1;
				Level_num <= 14;
				Level_value <= 6'b111111;
				cnt <= cnt+1;
			end	
			29:begin
				Sig_level_write <= 0;
				cnt <= cnt+1;
			end
			30:begin	  
				Sig_level_write <= 1;
				Level_num <= 15;
				Level_value <= 6'b111111;
				cnt <= cnt+1;
			end	
			31:begin
				Sig_level_write <= 0;
				cnt <= cnt+1;
			end
			32:begin	  
				Sig_level_write <= 1;
				Level_num <= 8;
				Level_value <= 8'b11111111;
				cnt <= cnt+1;
			end	
			33:begin
				Sig_level_write <= 0;
				cnt <= cnt+1;
			end
			endcase
		end
	end	
endmodule

